SIMULATION Optimization of the Acid Catalyst Concentration for Synthesis of Anti‐Cancer Agent Gamavuton‐0 by Using Mathematical and Statistical Software

3 References [ ] S. Mitra, N. Seifert, M. Zhang, Q. Sbi and K.S. Kim, Robust system design with built‐in soft‐error resilience,” EEE Des. Test Comput., pp. ‐‐ , Feb. . [ ] T. Karnik, P. azucha and J.Patel, Characterization of soft errors caused by single event upsets in CMOS processes,” EEE Trans., Dependable Secure Comput., vol. , No. , pp. 8‐‐ , . [ ] L.‐T. Wang, C.‐W. Wu and X. Wen, VLS test principles and architectures: design for testability, Morgan Kaufmann, . [ ] N. Bidokhti, SEU concept to reality allocation, prediction, mitigation ,” Reliability and Maintainability Symp, proceedings ‐ Annual. [ ] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger and L. Alvisi, Modeling the effect of technology trends on the soft error rate of combinational logic,” Proc. EEE ntl Conf. Dependable Syst. Networks, pp. 8 ‐‐ 8, . [ ] D.R. Blum, M.J. Myjak and J.G. Delgado‐Frias, Enhanced fault‐tolerant data latches for deep submicron CMOS,” Proc. EEE ntl Conf. Comput. Des., pp. 8‐‐ , . [ ] T. Calin, M. Nicolaidis and R. Velazco, Upset hardened memory design for submicron CMOS technology,” EEE Trans. Nuclear Sci., Vol. , No. , pp. 8 ‐‐ 8 8, Dec., . [8] R. Naseer and J. Draper, The DF‐DCE storage element for immunity to soft errors,” Proc. 8th ntl Midwest Symp. Circuit Syst., pp. ‐‐ , . [ ] R. Naseer and J. Draper, DF‐DCE: A scalable solution for soft error tolerant circuit design,” Proc. EEE ntl Symp. Circuits Syst., pp. 8 ‐‐ 8 , . [ ] A. Goel, S. Bhunia, . Mahmoodi and K. Roy, Low‐overhead design of soft‐error‐tolerant scan flip‐flops with enhanced‐scan capability,” Proc. Des. Automation Asia South Pacific Conf., pp. ‐‐ , . [ ] S. Mitra, M. Zhang, S. Waqas, N. Seifert, B. Gill and K.S. Kim, Combinational logic soft error correction,” Proc. EEE ntl Test Conf., pp.8 ‐‐8 , . [ ] M. Omana, Novel transient fault hardened static latch,” Proc. EEE ntl Test Conf., pp.88 ‐‐ 8 , . [ ] L. R. Rockett, Jr, An SEU‐hardened CMOS data latch design,” EEE Trans. Nucl. Sci., vol. , pp. 8 – 8 , Dec. 88. [ ] T. Monnier, F.M. Roche, J. Cosculluela, and R. Velazco, SEU testing of a novel hardened register implemented using standard CMOS technology,”EEE Trans. Nucl. Sci., vol. , no. , pp. – , Dec. . [ ] Y. Zhao and S. Dey, Separate dual‐transistor registers—A circuit solution for on‐line testing of transient error in UDSM‐C,” in Proc. EEE nt. On‐Line Test. Symp., , pp. – . [ ] Y. Komatsu, Y. Arima, T. Fujimoto, T. Yamashita and K. shibashi, A soft‐error hardened latch schemes for SoC in a nm technology and beyond,” Proc. EEE Custom ntegr. Circuit Conf., pp. ‐‐ , . [ ] K. Namba, T. keda and . to, Construction of SEU Tolerant Flip‐Flops Allowing Enhanced Scan Delay Fault Testing,” EEE Trans. Very Large Scale ntegr. Syst., Vol. 8, No. , pp. ‐ , Sep., . [ 8] Y. Lu, F. Lombardi, S. Pontarelli and M. Ottavi, Design and Analysis of Single‐ Event Tolerant Slave Latches for Enhanced Scan Delay Testing,” EEE Trans. Device Mater. Reliab., vol. , No. , pp ‐ , Mar. . [ ] [Online]. Available: http:ptm.asu.edu